1. Field of the Invention
The present invention relates to an internal voltage generation control circuit and an internal voltage generation circuit using the same, and more particularly to an internal voltage generation control circuit and an internal voltage generation circuit using the same, wherein, when a read or write command is input, the internal voltage generation control circuit outputs an internal voltage generation control signal during a suitable time, regardless of the frequency of an external clock signal.
2. Description of the Related Art
As the operating frequency of semiconductor memory devices such as DRAM has increased for high-speed operations, much attention has recently been given to reducing current consumption. The current consumption reduction is an essential requirement for designing semiconductor devices such as DRAM as the application of DRAM or the like has been extended to portable devices, without being limited to main memories of computers. A conventional circuit internal voltage generation circuit generates an internal voltage required for input and output operations after an active operation. Specifically, the conventional internal voltage generation circuit generates an internal voltage when a read or write command is input, and constantly supplies the internal voltage until a predetermined delay time expires after clock periods, corresponding to the sum of a latency and a burst length, elapse from the moment when the read or write command is input. However, since the delay time is fixed regardless of the operating clock frequency, the conventional internal voltage generation circuit has a problem in that, as the clock frequency increases, unnecessarily large current is supplied during the delay time, thereby increasing current consumption.
FIG. 1 illustrates the configuration of a conventional internal voltage generation control circuit, and FIGS. 2 and 3 are signal waveform diagrams illustrating the operation of the conventional internal voltage generation control circuit. The above problem of the conventional semiconductor device will now be described in detail with reference to FIGS. 1 to 3.
The conventional internal voltage generation control circuit shown in FIG. 1 operates in the following manner. As shown in FIG. 2, if a read or write command RD/WT is input synchronously with a rising edge of a clock CLK, a column active pulse signal CACTP is generated and input to a PMOS P12 and an NMOS N11 in the internal voltage generation control circuit. In addition, a column active signal CACT is generated and input to a delay unit 102 and a pulse generator 101.
The column active pulse signal CACTP is a signal that is generated when a read/write command RD/WT is input. The column active pulse signal CACTP is enabled synchronously with the input of the read/write command RD/WT, and serves as a source signal in generating a control signal CA_ACT for use in generating an internal voltage required for a read/write operation. The column active signal CACT is a signal which contains burst length information and allows a column operation such as a read or write operation of a bank of interest to be performed after a latency has elapsed from the moment when a read or write command RD/WT is input. The term “latency” refers to a time required to initiate a data read or write operation from the moment when a corresponding read or write command is input.
If the column active pulse CACTP is enabled (i.e., shifts from a low level to a high level) as a read/write command is input as shown in FIG. 2, the NMOS N11 is turned on so that a node LATB is pulled down to a low level. Then, a latch 103 latches the low level information during a predetermined time and outputs a high level signal. Accordingly, the internal voltage generation control signal CA_ACT is enabled (i.e., shifts to a high level), thereby controlling an internal voltage generation unit (not shown) to generate an internal voltage.
The pulse generator 101 receives a column active signal CACT, and generates and provides a signal RESETBP to the PMOS P11. The signal RESETBP is a signal that is enabled (i.e., shifts to a low level) at the moment when the column active signal CACT is disabled (i.e., shifts from a high level to a low level), i.e., when clock periods, which correspond to the sum of the latency and the burst length, expire. Until the clock periods expire, the PMOS P11 receives a high level signal and remains off, so that the output of the latch 103 maintains the previous state. The delay unit 102 delays the column active signal CACT by a predetermined delay time tDLT and outputs the delayed signal CACTFD as shown in FIG. 2.
If the column active signal CACT shifts from a high level to a low level as the clock periods, corresponding to the sum of the latency and the burst length, elapse after the read/write command is input, the PMOS P11 is turned on so that the node LATB is pulled up to a high level. Then, the latch 103 latches the high level information and outputs a low level signal through its output terminal. The low level signal is input to an input terminal A of a NOR gate NR11. At this time, the signal CACTFD output from the delay unit 102 remains high as shown in FIG. 2, and therefore the output signal of the NOR gate NR11 is low, so that the internal voltage generation control signal CA_ACT remains enabled (i.e., remains high).
If the signal CACTFD shifts to a low level as a delay time tDLT elapses from that moment when the clock periods expire, all input signals of the NOR gate NR11 are low, so that the internal voltage generation control signal CA_ACT is disabled (i.e., shifts to a low level).
As described above, the conventional internal voltage generation control circuit enables the internal voltage generation control signal CA_ACT if a read/write command is input, and then disables the signal CA_ACT after a time interval, which corresponds to the sum of the latency, the burst length, and the delay time (tDLT), elapses, thereby allowing an active-operation internal voltage to be supplied during the time interval (i.e., latency+burst length+tDLT).
The delay time tDLT determines how long the internal voltage generation control signal CA_ACT remains enabled after the column active signal CACT drops to a low level. As shown in FIG. 3, if another read/write command RD/WT is input at a time X before the column active signal CACT drops to a low level in the case where the delay time tDLT is not employed, the internal voltage generation control signal CA_ACT shifts to a high level immediately after shifting from a high level to a low level, which causes internal voltage instability. The delay time tDLT is used to prevent this phenomenon.
However, since the delay time tDLT is fixed to about 30 ns, the conventional internal voltage generation control circuit has a problem in that unnecessary current consumption is caused as the clock frequency increases. That is, if the clock frequency is increased, a time interval corresponding to the latency and the burst length is decreased even if the number of clock periods corresponding to the sum of the latency and the burst length is constant. Accordingly, a delay time, required to prevent the internal voltage generation control signal CA_ACT from alternating between the high and low levels as described above, is also decreased. However, in the conventional internal voltage generation control circuit, the internal voltage generation control signal CA_ACT remains enabled for an excessively long time since the delay time tDLT is fixed regardless of the clock frequency, thereby causing unnecessarily large current consumption.